12809 ms 20081209-s00004 no.a1394-1/9 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 LV5052V overview the LV5052V is a high efficiency dc/dc converter controller with 2-channels ic adopting a synchronous rectifying system. incorporating numerous functions on a single chip w ith easy external setting, it can be used for a wide variety of applications. this device is optimal for use in internal power supply systems which are used in electronic devices, lcd-tvs, dvd recorders, etc. functions ? step-down dc/dc converter controller with 2-channel ? built-in input uvlo circuit, over current detection functio n, soft-start/soft-stop function and start-up delay circuit ? built-in output voltage monitor function (under vo ltage protection with power good and timer latch) ? 180 degree interleaving operation during 1-phase to 2-phase ? synchronized operation is possible (master-slave operation is possible when using plural devices) specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in 18 v output peak current i out 1.0 a allowable power dissipation pd max mounted on a specified board *1 1.0 w operating temperature topr -20 to 85 c storage temperature tstg -55 to +150 c allowable terminal voltage *2 1 hdrv1,2, cboot1,2 25 v 2 between hdrv1,2, cboot1,2 and sw1,2 6.5 v 3 v in , ilim1,2, rsns1,2, sw1,2, pgood1,2 18 v 4 vlin5, v dd , ldrv1,2 6.5 v 5 comp1,2, fb1,2, ss1,2, uv_delay,td1,2, ct, clko vlin5+0.3 v *1: specified board: 114.3mm 76.1mm 1.6mm, glass epoxy board . *2: the allowable terminal voltage, the sgnd+pgnd pin becomes a standard except for no .2 of the allowable terminal voltage abou t no.2 of the allowable terminal voltage, the sw pin becomes a standard. bi-cmos ic dc/dc converter controller built-in 2-channels orderin g numbe r : ena1394 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV5052V no.a1394-2/9 recommended operating condition at ta = 25 c parameter symbol conditions ratings unit supply voltage v in 9.4 to 16 v electrical characteristics at ta = 25 c, v in =12v, unless especially specified. ratings parameter symbol conditions min typ max unit system reference voltage for comparing v ref 0.838 0.840 0.848 v supply current 1 i cc 1 td1,2 = 5v (except for the ciss charge) 4 6 8 ma supply current 2 i cc 2 td1,2 = 0v 0.8 1.4 2.0 ma 5v supply voltage vlin5 ivin5 = 0 to 10ma 5.10 5.30 5.50 v over-current sense comparator offset v cl os -5 +5 mv over-current sense reference current source i cl v in = 10 to 14v 75 85 95 a soft start source current i ss sc td = 5v -1.8 -3.5 -7.0 a soft start sink current i ss sk td = 0v 0.2 1.0 ma soft start clamp voltage v ss t0 1.2 1.6 2.0 v uv_delay source current i sc uvd uv_delay = 2v -4.3 -8.6 -17.2 a uv_delay sink current i sk uvd uv_delay = 2v 0.2 1.0 ma uv_delay threshold voltage v uvd 1.5 2.4 3.5 v uv_delay operating voltage v uvp 100% at vfbx = v ref 77 82 87 % vuvp detection hysteresis v uvp 4 % over-voltage detection v o vp 100% at vfbx = v ref 113 118 123 % output discharge transistor on resistance v sw on 5 10 20 output part cboot leakage current i cboot vcboot = vsw + 6.5v 10 a hdrvx ldrvx source current i sc drv 1.0 a hdrvx ldrvx sink current i sk drv 1.0 a hdrvx lower on resistance r h drv i out = 500ma 1.5 2.5 ldrvx lower on resistance r l drv i out = 500ma 1.5 2.5 synchronous on prevention dead time 1 t dead 1 ldrv off hdrv on 50 ns synchronous on prevention dead time 2 t dead 2 hdrv off ldrv on 120 ns oscillator oscillation frequency f osc ct=130pf 280 330 380 khz oscillation frequency range f osc op 250 1100 khz maximum on duty d on max ct=130pf 82 % minimum on time t on min ct=130pf 100 ns upper-side voltage saw- tooth wave v saw h f osc =300khz 2.75 3.2 v lower-side voltage saw-tooth wave v saw l f osc =300khz 1 1.2 v on time difference between ch1 to ch2 tdead 5 % continued on next page.
LV5052V no.a1394-3/9 continued from preceding page. ratings parameter symbol conditions min typ max unit error amplifier error amplifier input current i fb -200 -100 200 na comp pin source current i comp sc -100 -18 a comp pin sink current i comp sk 18 100 a error amplifier gm gm 500 700 900 umho current detection amplifier gain gisns 5 6.4 7.8 logic output power good low level source current i pwrgd l v pgood = 0.4v 0.5 1.0 ma power good high level leakage current i pwrgd h v pgood = 12v 10 a tp pin threshold voltage v on td when the voltage of the td pin rises 1.5 2.6 3.5 v tp pin high impedance voltage v td h when v in and vlin5 pins are set to open 4.5 5.2 5.5 v td pin charge source current i td sc -1.8 -3.5 -7.0 a td pin discharge sink current i td sk 0.2 1.0 ma clko high level voltage v clko h i clko = 1ma 0.7v5lin v clko low level voltage v clko l i clko = 1ma 0.3v5lin v protection function v in uvlo release voltage v uvlo 3.5 4.1 4.3 ma uvlo hysteresis v uvlo 0.4 a
LV5052V no.a1394-4/9 package dimensions unit : mm (typ) 3191b pin assignment 30 29 28 27 26 25 24 23 22 21 1 sw1 2 hdrv1 3 cboot1 4 vlin5 5 rsns1 6 7 ilim1 8 td1 20 19 14 13 12 11 9 10 pgnd ldrv1 uv_delay ct clko ss1 v in 18 17 16 15 v dd sgnd fb1 LV5052V top view comp1 pgood1 hdrv2 ldrv2 sw2 cboot2 comp2 fb2 rsns2 ilim2 td2 ss2 pgood2 sanyo : ssop30(275mil) 9.75 5.6 7.6 0.22 0.65 (0.33) 1 15 16 30 0.5 0.15 1.5max 0.1 (1.3) 0 pd max - ta -20 1200 600 200 800 400 20 04060 80 100 494 85 1000 950 ambient temperature, ta -- c allowable power dissipation, pd max -- mw specified board: 114.3 76.1 1.6mm 3 glass epoxy board.
LV5052V no.a1394-5/9 block diagram v in 5v reg (always on) internal bias typ 85 a vlin5 5.3v vin ilim comp sense amp ilim1 rsns1 cboot1 hdrv1 r s q q shifter & latch sw1 shoot through protection sequencer v dd ldrv1 active discharge rdson = 15 pwm logic skip control sd por pwm comp corrective ramp 0 deg ss1en d vref 1.6v sd 3.5 a 3.5 a por 2.6v cont1 uv1 ov1 0.82vref 1.18vref comp1 fb1 ch1 output ss1 td1 typ 85 a vin ilim comp sense amp ilim2 rsns2 cboot2 hdrv2 r s q q shifter & latch sw2 shoot through protection sequencer ldrv2 active discharge rdson = 15 pwm logic skip control sd pwm comp corrective ramp 180 deg ss2en d vref 1.6v sd 3.5 a 3.5 a por 2.6v cont2 uv2 ov2 0.82vref 1.18vref comp2 fb2 ch2 output ss2 td2 ch1 output ch2 output pgnd r s q q 0v uv timeout 2.6v 1 s delay 9 a cont1 cont2 por ov1 ov2 ss1en d ss2en d uv1 uv2 pgood1 pgood2 uv_delay 0 deg 180 deg osc 300khz ct clko sync. pulse out 0v 5v sgnd vlin5 vin voltage and current generator current bias bg reference bg iref input power supply vref 0.84v error amp error amp 9.0v /8.0v 4.5v /4.0v vref
LV5052V no.a1394-6/9 pin functions pin no. pin name description 1 v dd power supply pin for the gate drive of an external lower-side mos-fet. this pin is connected to the vlin5 pin through a filter. 2 ldrv the gate drive pin of an external lower-side mos-fet of channel 1. this pin has the signal input part for prevention of short-through of both the upper and lower mos-fets. when the voltage of this pin becomes less than 1v, the hdrv pin is turned on. 3 hdrv1 the gate drive pin for an external upper side mos-fet of channel 1. 4 sw1 this pin is connected with the switching node of channel 1. a source of an external upper side mosfet and a drain of an external lower side mos-fet are connected with this pin. this pin become s the return current pa th of the hdrv pin. this pin is connected with a transistor drain of the discharge mos-fet for soft stop in the ic (typical 30 ). also, this pin has the signal output part for the short through prevention of both the upper and lower mos-fets. when this terminal voltage becomes 1v or less for pgnd, the ldrv pin is turned on. 5 cboot1 the bootstrap capacity connection pin of channel 1. the gate drive power of upper mosf et is provided by this pin. this pin is connected to the v dd pin through a diode and is connected to the sw pin through the bootstrap capacity. 6 vlin5 the output pin of an in ternal regulator of 5v. the current is provided by the v in pin. also, power supply of the control circuit in the ic is pr ovided by this pin. connect an output capacitor of 4.7 f between this pin and sgnd. a regulator of 5v operates, even if the ic is in the standby state. this pin is monitored by an uvlo function and the ic starts by the voltage of 4.5v or more (t he ic is off by the voltage of 4.0v or less.) 7 comp1 the phase compensation pin of channel 1. the output of an internal transforme r conductance amplifier is connected. connect an external phase compensation circuit between this pin and sgnd. 8 fb1 feed back input pin of channel 1. the minus terminal (-) of the trans conductance amplifier is connected. the voltage generated when the output voltage was divided by a resistor is input into this pin. the converter operates so that this pin becomes an internal reference voltage (v ref =0.8v). also, this pin is monitored by the comparators uvp and ovp. when the voltage of this pin becomes less than 82% of the set voltage, the pgood pin is low level. a timer of the uv_delay function operates. also, when the volt age of this pin becomes more than 117% of the set voltage, the ic latches off. 9 rsns1 channel 1 side input pin of the over current dete ction comparator / the curr ent detection amplifier. to detect resistance, this pin is connected to the under si de of a resistor for the current detection between the v in pin and the drain of the upper mos-fet. also, to use the on resistance of mos-fet for the current de tection, connect this pin to the source of the upper mos-fet. to prevent the common impedance of main current to the detection-voltage, this pin is connected by independent wiring. 10 ilim the pin to set the trip point fo r over current detection of channel 1. since the sink current source of 85 a (ilim) is connected in the ic, the over-current detection voltage (ilim rlim) is generated by connecting a resistor rlim between this pin and the v in pin. the over-current is detected by comparing the voltage between the v in pin and the ilim pin to the current detection resistance rsns or both end voltage of the upper mosfet. 11 td start-up delay pin of channel 1. the time until the ic starts after releasing por is set by connecting a capacitor between this pin and sgnd. after releasing por, an external capacitor is ch arged up by the constant current source of 3.5 a in the ic. when this terminal voltage becom es 2.6v or more, the ic starts. also, when th is terminal voltage becomes 2.6v or less, the ic becomes the standby state. if external capacitor is not connected, the ic instant ly starts after releasing por. 12 ss1 the pin to connect a capacit or for soft start of channel 1. after releasing por, when the voltage of the td pin becomes 2. 6v or more, the ss1 pin is charged by an internal constant current source of 3.5 a. since this pin is connected to the positive (+) input of the transformer c onductance amplifier, the ramp-up wave form of the ss pin become s the ramp-up wave form of the output. during por operations and after the uv_delay time-out, the ss1 pin is discharged 13 pgood the power good pin of channel 1. the open drain mos- fet of the withstand of 28v is connected in the ic. when the output voltage of channel 1 is less than -13% for the setup voltage, the low level is output. this pin has hysteresis of about (v ref 4.0%). 14 uv_delay common uvp delay pin to channel 1 and channel 2. by connecting a capacitor between this pin and sgnd, the time un til the ic latches off after detecting the uvp state can be set. also, after channel 1 or channel 2 te rminated the soft-start function, when th e output voltage becomes 82% or less for the setup voltage, an external capacitor is c harged by the constant current source of 8.6 a in the ic. when this terminal voltage becomes 2.6v or more, the ic is latched off. if an external capacitor is not c onnected, the ic is instantly latched off after detecting the uvp state. also, when this pin is shorted to gnd, the uv_delay function is not operated. continued on next page.
LV5052V no.a1394-7/9 continued from preceding page. pin no. pin name description 15 v in power supply pin of the ic. this pin is observed by the uvlo function and ic starts by 9.0v or more. (after starts, stop by 8.0v or less. ) 16 clko the clock output pin. the clock that synchronized to the oscillation waveform of the ct pin is output. to synchronize two or more LV5052Vs, the clko pin of the devic e that becomes a master is connected to the ct pin of the device that becomes a slave. when two or more the devices are synchronized and the start-up timing is changed by using the td pin between each device, the earliest st art-up device is determined as the master. 17 ct the pin to connect an external capacitor for the osci llator. connect a capacitor between this pin and sgnd. when a capacitor of 130pf is connected between this pin and gnd, the oscillation frequency can be set up by 330khz. also, this pin is applied by an external clock signal. the pwm operation is performed by t he frequency of applied clock signal. when an external clock signal is applied, the rectangular wave of 0v in low level and from 0v / 3.3v to 5v in high level is applied. the rectangular wave source needs the fan-out of 1ma or more. 18 pgood2 the power good pin of channel 2. 19 ss2 the pin to connect a capacit or for soft start of channel 2. 20 td2 start-up delay pin of channel 2. 21 ilim2 the pin to set the trip point fo r over current detection of channel 2. 22 rsns2 channel 2 side input pin of the over current dete ction comparator / the curr ent detection amplifier. 23 fb2 feed back input pin of channel 2. 24 comp2 the phase compensation pin of channel 2. 25 sgnd the system ground of the ic. the refer ence voltage is generated based on this pin. this pin is connected to the power supply system ground. 26 cboot2 the bootstrap capacity connection pin of channel 2. 27 sw2 this pin is connected with the switching node of channel 2. 28 hdrv2 the gate drive pin for an external upper side mos-fet of channel 2. 29 ldrv2 the gate drive pin of an external lower-side mos-fet of channel 2. 30 pgnd power ground pin. this pin becomes the return current path of the ldrv pin.
LV5052V no.a1394-8/9 start-up sequence each signal control timing at power supply on is as below. v in vlin5 td ss vout pgood 9v typ 4.5v typ 2.4v typ 0.8v vout 82% v in =12v vlin5=5v td=5v ss=1.6v vout=vout 100% uvlo release * * starts charging the td at the trigger point of either vin > 9v(typ) or vlin5 > 4.5v(typ), whichever is later. protection operate sequence (1) latch-off release by uvlo the signal control timing diagram for resetting the latch-off condition using uvlo is shown below. v in vlin5 td ss vout pgood v in =12v vlin5=5v td=5v ss=1.6v vout=vout 100% 8v typ 9v typ 2.4v typ 0.8v vout 82% vout 118% vout 82% ovp restart td discharge start (2) latch off release by td the signal control timing diagram for resetting the latch-off condition using uvlo is shown below. v in vlin5 td ss vout pgood v in =12v vlin5=5v td=5v ss=1.6v vout=vout 100% 2.4v typ 0.8v vout 82% vout 118% vout 82% ovp td discharge start
LV5052V ps no.a1394-9/9 synchronized operation a recommended circuit for synchronizing the LV5052V is shown below. clko v in ct 130pf v in ct 10k v in ct 10k master slave v in (typ 12v) on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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